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Tasks Include ATPG pattern generation ATPG pattern verification Debug failed test vectors Create patters for stuckat and atspeed transition delay Required Extensive experience using Tetramax Extensive DFT Test Vector Generation Experience
Attention all top performingIC design verification engineers I am helping my client to build a verification team for a new product line at their established San Jose CA office Theyre working on some industry leading designs and you would...
Skills/Experience: - Requires 5 to10 years industry experience in full custom analog and/or mixed signal transistor-level design. - Combination of low voltage/low power design and high voltage output capability techniques are emphasized -...
Responsibilities You will be contributing to the verification effort of a complex chip sub-system and or blocks You will define chip level verification strategies test planning and develop all necessarytools and scripts to enable...
Job Description This person will write behavioral Verilog and VerilogAMS models of RFanalog blocks for functional verification of radio chips Responsibilities The primary duty will be to 1 Interrogate designers to extract modeling...
tion of tool/language profilers) -configure database servers (e.g. MySQL) We are unable to sponsor H1B candidates or consider third party sponsors at this time. Kathy Stokes Kathy@Xpeerant.com (512)551-4155 Austin...
ning on top of TCP digital logic simulation OVM UVM VMM System Verilog Specman C We are unable to sponsor H1B candidates or consider third party sponsorsat this time Kathy StokesKathy Xpeerant com 512 551-4155 Austinhttp www linkedin com...
Attention all top performing IC design verification engineers I am helping my client to build a verification team for a new product line at their established San Jose CA office Theyrsquore working on some industry leading designs and you...
Calibre, MBIST Architect, DFT Advisor Spyglass RTL Coding: Verilog, System VerilogScripting: Python TCL, AWK, PERL, UNIX ShellPlease send resume to keith@xpeerant.com [ mailto:keith@xpeerant.com ] Tired of getting RIPPED-OFF by 'those'...
Responsibilities - Complete responsibilty for PD of hierarchical blocks - Responsible for floorplaning P R timing DRC LVSSkills Experience Experience with EDA tools ICC and methodologies for all tasks described above EDA Tool and Unix...
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