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Tensilica jobs - Palo Alto, CA

Viewing 1 - 8 of 15 jobs

  • Principal Design Engineer

    Cadence Design Systems - San Jose, CA

    Debug backend flow for Tensilica cores in 16nm/14nm/10nm advanced process geometries. Provide expert guidance on use of backend tools and flows. Participate in benchmarking PPAs for customer engagements. Position Requirements The candidate...

    8 days ago from Cadence Design Systems, Inc.

  • Principal Design Verification Engineer

    Cadence Design Systems - San Jose, CA

    Jose, CA Functional Area:Engineering Cost Center:Tensilica India R&D Position Type:Regular Education ... * Apply withLinkedIn Position Description Cadence’s IPG Tensilica processors are based on the proven Xtensa...

    30+ days ago from Cadence Design Systems, Inc.

  • Imaging and Vision Multiprocessor Architect

    Cadence Design Systems - San Jose, CA

    Jose, CA Functional Area:Engineering Cost Center:Tensilica US R&D Position Type:Regular Education ... detailed product deliverables for an MP subsystem on the Tensilica/Cadence imaging and vision architecture. This...

    30+ days ago from Cadence Design Systems, Inc.

  • Sr. DSP Processor Datapath Architect

    Cadence Design Systems - San Jose, CA

    control). The automated design tools behind all of Tensilica’s application-specific processor cores enable rapid ... to meet specific data-plane performance targets. Tensilica’s processors power top tier semiconductor companies,...

    7 days ago from Cadence Design Systems, Inc.

  • Principal CM Engineer-Project Lead

    Cadence Design Systems - San Jose, CA

    Jose, CA Functional Area:Engineering Cost Center:Tensilica US R&D Position Type:Regular Education ... Generator in the space of automation, build and release. Tensilica has a sophisticated online system for configuring...

    22 days ago from Cadence Design Systems, Inc.

  • Principal Design Engineer - Datapath Design

    Cadence Design Systems - San Jose, CA

    Jose, CA Functional Area:Engineering Cost Center:Tensilica US R&D Position Type:Regular Education ... of DSP instructions and specialized DSP hardware using Tensilica processor description languages (TIE), and tools...

    30+ days ago from Cadence Design Systems, Inc.

  • Sr. Android Software Engineer

    Cadence Design Systems - San Jose, CA

    low-power audio offload software framework for Tensilica HiFi audio DSPs for Android and other platforms. Develop methods and participate in standards for routing compressed audio (deep tunneling) and other offload processing for ultra low...

    7 days ago from Cadence Design Systems, Inc.

  • Senior Principal Design Engineer - Datapath Design

    Cadence Design Systems - San Jose, CA

    The automated design tools behind all of Tensilica’s application-specific processor cores enable rapid customization ... specific data-plane performance targets. Tensilica’s processors power top tier semiconductor companies, innovative...

    7 days ago from Cadence Design Systems, Inc.