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ASIC Design Verification Engineer, System Verilog, UVM, OVM ASIC Design Verification Engineer, System Verilog, RTL, VHDL ... design - verification experience. We need mid-level through senior candidates, we're building an entire team! * Expert...
This company ROCKS! Job Description: The Sr. Digital Design Engineer will be responsible for design, development, ... design, verification, synthesis, timing analysis, design for test, backend verification and silicon debug.
seeking a senior level pre-silicon Verification Tools Engineer for front-end design flow support and to aid in the ... You would actually be the primary engineer (POC) who interfaces with the user community and tool-owners/IT...
- United States As a CAD engineer supporting our physical verification methodology, you will develop & integrate decks ... rule decks. You will also be responsible for all physical verification methodology, including development,...
The Position Senior Digital Design Engineer (EK) Semiconductors Engineering - Electrical Full-time United States - Texas ... design, verification, synthesis, timing analysis, design for test, backend verification and silicon debug.
Sr. CAD Engineer-Physical Verification branch: Corporate Engineering Job Type: Full-Time Location: Austin, TX ... Experience developing/supporting physical verification and extraction flows for use by a globally distributed IC design...
SENIOR ASIC VERIFICATION ENGINEER, SECURITY IP Job ID 1569822 Location US, TX, Austin Description SENIOR ASIC ... VERIFICATION ENGINEER, SECURITY IP #1569822 As a Security Verification Engineer at NVIDIA, you will verify the design...
areas: *Architecture andDesign of Digital Filters *RTL Design usingVerilog/System Verilog *Top-levelSynthesis and ... latestEDA tools to continually improve quality and design cycles Verification of complexSystem-on-Chip (SoC)...
Sr Verification Engineer DDR Design IP Job ID #:7455 Location:Austin, TX Functional Area:Engineering Cost Center:D DDR ... This position is responsible for verification of DDR Design IP using a SystemVerilog-based coverage-driven...
US, TX, Austin Description SENIOR TEGRA SOC VERIFICATION ENGINEER #1588487 RESPONSIBILITIES: - Design Verification of ... with 3+/5+ years of experience in ASIC design or verification - Proficient in Verilog HDL, System Verilog,...
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