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Dft Logic Design Engineer jobs - San Jose, CA

Viewing 1 - 10 of 124 jobs

  • Sr Applications Engineer

    Cadence Design Systems - San Jose, CA

    Requirements: * Design experience should include ASIC design using industry-standard hardware description ... ASIC Design Implementation , Synthesis, Design Constraints, DFT and Deep Static Timing Analysis for a number of ASIC...

    30+ days ago from Cadence Design Systems, Inc

  • Principal Application Engineer

    Cadence Design Systems - San Jose, CA

    Requirements: * Design experience should include ASIC design using industry-standard hardware description ... ASIC Design Implementation , Synthesis, Design Constraints, DFT and Deep Static Timing Analysis for a number of ASIC...

    30+ days ago from Cadence Design Systems, Inc

  • DFT Engineer

    NVIDIA - Santa Clara, CA

    may span across several DFT areas including: Memory Test design and verification JTAG, and Boundary-Scan design and ... As a DFT engineer, you will be working on cutting edge DFT/ATE test methods and designs Solid background/course...

    30+ days ago from Doostang

  • Senior ASIC Engineer - DDR2/3 - RTL

    Cyient - San Jose, CA

    chip synthesis, writing constraints interfacing with logic design engineers, implementing low power synthesis ... STA, cleaning up constraints working with logic design and DFT teams Good Logic Design basics...

    30+ days ago from Sologig

  • Principal RTL Logic Designer (CPU start-up)

    Quantum Solution - Santa Clara, CA

    inputs will include micro-architecture specification and logic design for a high-performance, low-power CPU core. As ... Work with design team members across disciplines (Logic, Circuits, PD, DFT) to implement and validate physical design on...

    2 days ago from Quantum Solution

  • SENIOR DFT ENGINEER

    NVIDIA - Santa Clara, CA

    SENIOR DFT ENGINEER #1752080 As a DFT engineer at NVIDIA, you'll be responsible for cutting edge DFT involving ... required, MSEE preferred. - 4 to 5 years of experience in DFT / design field. - Strong logic Design and verification...

    2 days ago from Nvidia

  • Design Engineer

    Altera - San Jose, CA

    a Senior Level Design Engineer, you will be involved in the design, verification, and integration of Altera's next ... architecture specification and planning, logic/DFT/DFX design and verification, synthesis/STA and timing closure,...

    30+ days ago from Altera

  • Senior Digital Design Engineer

    Marvell Technology Group - Santa Clara, CA

    includes logic design, DFT planning and implementation, logic synthesis, power optimization, static timing closure and sign-off. Candidates will also work closely with product/analog/backend teams for IP integration, and P&R engineers for...

    30+ days ago from Marvell Technology Group

  • Senior Digital Design Engineer

    Results Center - Santa Clara, CA

    * Solid background in ASIC development through the entire design cycle * Good communication skills Description ... includes logic design, DFT planning and implementation, logic synthesis, power optimization, static timing closure...

    30+ days ago from The Results Center

  • Senior Digital Design Engineer

    Marvell - Santa Clara, CA

    * Solid background in ASIC development through the entire design cycle * Good communication skills Description ... includes logic design, DFT planning and implementation, logic synthesis, power optimization, static timing closure...

    30+ days ago from Marvell

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